1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a circuit for synchronizing a phase between two clocks, and a delay locked loop circuit of a semiconductor device, to which the circuit is applied.
2. Description of the Related Art
A synchronous semiconductor memory device such as a double data rate synchronous DRAM (DDR SDRAM) transmits data to an external device outside of the semiconductor memory device using an internal clock synchronized with an external clock inputted from the external device such as a memory controller.
This clock structure and configuration is implemented because the temporal synchronization between an external clock applied from the memory controller to the memory device and data outputted from the memory device is very important for the purpose of stable transmission between the memory device and the memory controller.
In the example as described above, the data outputted in the memory device is outputted in synchronization with the internal clock. The internal clock is initially applied to the memory device in the state where the internal clock is synchronized with the external clock, but the internal clock is delayed while passing through each component in the memory device. Therefore, the internal clock is outputted to the outside of the memory device in the state where the internal clock is not synchronized with the external clock.
Accordingly, to perform stable transmission of data outputted from the memory device, the internal and external clocks is to be synchronized with each other so that the internal clock is exactly positioned at an edge or center of the external clock applied from the memory controller when transmitting data on a bus.
A phase locked loop (PLL) circuit and a delay locked loop (DLL) circuit are used as clock synchronization circuits for performing the function described above.
In an example where the frequencies of the external and internal clocks are different from each other, the PLL circuit is frequently used, which performs a frequency rearranging function. However, in an example where the frequencies of the external and internal clocks are identical to each other, the DLL circuit is frequently used. The DLL circuit also may be implemented in a relatively small area without being influenced by noise, as compared with the PLL circuit.
More specifically, since the frequencies of the internal and external clocks used in the semiconductor memory device are identical to each other, the DLL circuit is frequently used as a clock synchronization circuit.
FIG. 1 is a block diagram illustrating a DLL of a semiconductor device.
Referring to FIG. 1, the general DLL of the semiconductor device includes a phase detector 120, a clock delay 100, and a replica modeling 140. The phase detector 120 compares the phase of a source clock REFCLK with the phase of a feedback clock FBCLK, and generates a phase comparison signal FINE and a phase difference detection signal LOCK_STATE corresponding to the compared result. The clock delay 100 delays the source clock REFCLK through a variable delay line and outputs a delay locked clock DLLCLK. In the variable delay line, a delay amount is controlled in response to the phase difference detection signal LOCK_STATE, and a change direction of the delay amount is controlled in response to the phase comparison signal FINE. The replica modeling 140 delays the delay locked clock DLLCLK by a delay amount tREP obtained by modeling an input delay path of the source clock REFCLK and an output delay path of the delay locked clock DLLCLK, and the replica modeling 140 outputs the delayed delay locked clock DLLCLK as the feedback clock FBCLK.
Here, the clock delay 100 includes a variable delay line and a controller. The variable delay line delays the source clock REFCLK by a delay amount corresponding to a delay control signal DLY_CONT, and the variable delay line outputs the delayed source clock REFCLK as the delay locked clock DLLCLK. The controller generates the delay control signal DLY_CONT in response to the phase comparison signal FINE and the phase difference detection signal LOCK_STATE.
FIG. 2 is a circuit diagram illustrating a detailed configuration of a conventional phase comparator of the DLL circuit of the semiconductor device illustrated in FIG. 1.
Referring to FIG. 2, the related art phase comparator 120 includes a first phase detector 122, a second phase detector 124, a third phase detector 126, and a phase difference detection signal generator 128. The first phase detector 122 detects the phase of a feedback clock FBCLK based on the phase of a source clock REFCLK. The second phase detector 124 detects the phase of a clock FBCLKd obtained by delaying the feedback clock FBCLK by a set delay amount DELAY based on the phase of the source clock REFCLK. The third phase detector 126 detects the phase of the feedback clock FBCLK based on the clock REFCLKd obtained by delaying the source clock REFCLK by the delay amount DELAY. The phase difference detection signal generator 128 determines the logic level of a phase difference detection signal LOCK_STATE corresponding to a phase difference between the source clock REFCLK and the feedback clock FBCLK in response to signals FINE, COARSE1, and COARSE 2 respectively outputted from the first to third phase detectors 122, 124 and 126.
Here, the phase difference detection signal generator 128 includes a first phase difference detector 1282, a second phase difference detector 1284, and a phase difference detection signal output 1288. The first phase difference detector 1282 detects whether or not the phase of the feedback clock FBCLK is within the phase difference corresponding to the delay amount DELAY in response to the signal FINE outputted from the first phase detector 122 and the signal COARSE1 outputted from the second phase detector 124. The second phase difference detector 1284 detects whether or not the phase of the feedback clock FBCLK is within the phase difference corresponding to the delay amount DELAY in response to the signal FINE outputted from the first phase detector 122 and the signal COARSE2 outputted from the third phase detector 126. The phase difference detection signal output 1288 outputs a phase difference detection signal LOCK_STATE having a logic level that is determined in response to an output signal DET1 of the first phase difference detector 1282 and an output signal DET2 of the second phase difference detector 1284.
FIG. 3 is a timing diagram illustrating an operation of the conventional phase comparator illustrated in FIG. 2.
Referring to FIG. 3, the related art phase comparator 120 illustrates timing diagrams of examples (A), (B) and (C). In example (A), the phase difference between the source clock REFCLK and the feedback clock FBCLK is greater than the phase difference corresponding to the set delay amount DELAY. In example (B), the phase difference between the source clock REFCLK and the feedback clock FBCLK is smaller than the phase difference corresponding to the set delay amount DELAY. In example (C), a jitter occurs in the case (B) where the phase difference between the source clock REFCLK and the feedback clock FBCLK is smaller than the phase difference corresponding to the set delay amount DELAY, and therefore, the state of the case (B) is changed into a state where the phase difference between the source clock REFCLK and the feedback clock FBCLK is greater than the phase difference corresponding to the set delay amount DELAY.
Referring to example (A), the logic level of the source clock REFCLK at a rising edge of the feedback clock FBCLK will be described so as to detect the phase of the feedback clock FBCLK based on the phase of the source clock REFCLK. As shown with reference to {circle around (1)}, the logic level of the source clock REFCLK becomes a non-activated state as logic ‘low’ so that the output signal FINE of the first phase detector 122 becomes the logic ‘Low.’ Next, the logic level of the source clock REFCLK at a rising edge of a clock FBCLKd obtained by delaying the feedback clock FBCLK by the set delay amount DELAY will be described so as to detect the phase of the clock FBCLKd obtained by delaying the feedback clock FBCLK by the set delay amount DELAY. As shown with reference to {circle around (2)}, the logic level of the source clock REFCLK becomes a non-activated state as logic ‘Low’ so that the output signal COARSE1 of the second phase detector 124 becomes the logic ‘Low.’ Next, the logic level of the clock REFCLKd obtained by delaying the source clock REFCLK by the set delay amount DELAY at a rising edge of the feedback clock FBCLK will be described so as to detect the phase of the feedback clock FBCLK based on the clock REFCLKd obtained by delaying the source clock REFCLK by the set delay amount DELAY. As shown with reference to {circle around (3)} the logic level of the clock REFCLKd becomes a non-activated state as logic ‘Low’ so that the output signal COARSE2 of the third phase detector 126 becomes the logic ‘Low.’
As such, in example (A) where the phase difference between the source clock REFCLK and the feedback clock FBCLK is greater than the phase difference corresponding to the set delay amount DELAY, the output signals FINE, COARSE1 and COARSE1 of the first to third phase detectors 122, 124 and 126 all become logic ‘Low,’ and therefore, the phase difference detection signal LOCK_STATE also maintains the non-activated state as logic ‘Low.’ Thus, the interval for changing the phase of the feedback clock FBCLK becomes a relatively high state so as to synchronize the phases of the source clock REFCLK and the feedback clock FBCLK with each other, and accordingly, the example (A) can be moved at a time to the case (B) where the phase difference between the source clock REFCLK and the feedback clock FBCLK is smaller than the phase difference corresponding to the set delay amount DELAY. In example (B), the interval for changing the phase of the feedback clock FBCLK becomes a relatively high state meaning that the phase of the feedback clock FBCLK is changed into a coarse operation mode in a general DLL circuit. Generally, the phase of the feedback clock FBCLK is changed for each delay amount corresponding to two unit delays every update period.
First, the logic level of the source clock REFCLK at a rising edge of the feedback clock FBCLK will be described so as to detect the phase of the feedback clock FBCLK based on the phase of the source clock REFCLK. As shown with reference to {circle around (1)}, the logic level of the source clock REFCLK becomes a non-activated state as logic ‘Low’ so that the output signal FINE of the first phase detector 122 becomes the logic ‘Low.’ However, the logic level of the source clock REFCLK at a rising edge of a clock FBCLKd obtained by delaying the feedback clock FBCLK by the set delay amount DELAY will be described so as to detect the phase of the clock FBCLKd obtained by delaying the feedback clock FBCLK by the set delay amount DELAY. As shown with reference to {circle around (2)}, the logic level of the source clock REFCLK becomes an activated state as logic ‘High’ so that the output signal COARSE1 of the second phase detector 124 becomes logic ‘High.’ Next, the logic level of the clock REFCLKd obtained by delaying the source clock REFCLK by the set delay amount DELAY at a rising edge of the feedback clock FBCLK will be described so as to detect the phase of the feedback clock FBCLK based on the clock REFCLKd obtained by delaying the source clock REFCLK by the set delay amount DELAY. As shown with reference to {circle around (3)}, the logic level of the clock REFCLKd becomes a non-activated state as logic ‘Low’ so that the output signal COARSE2 of the third phase detector 126 becomes logic ‘Low.’
As such, in example (B) where the phase difference between the source clock REFCLK and the feedback clock FBCLK is smaller than the phase difference corresponding to the set delay amount DELAY, the output signals FINE and COARSE 2 of the first and third phase detectors 122 and 126 become logic ‘Low,’ and the output signal COARSE1 of the second phase detector 124 becomes logic ‘High.’ Therefore, the phase difference detection signal LOCK_STATE is also changed from the non-activated state as logic ‘low’ to the activated state as logic ‘High.’ Thus, the interval for changing the phase of the feedback clock FBCLK is to be in a relatively low state so as to synchronize the phase of the source clock REFCLK and the phase of the feedback clock FBCLK with each other. In this example, the interval for changing the phase of the feedback clock FBCLK is to be in a relatively low state meaning that the phase of the feedback clock FBCLK is changed into a fine operation mode in the general DLL circuit. Generally, the phase of the feedback clock FBCLK is changed for each delay amount smaller than one unit delay every update period.
For reference, although the update period corresponding to a time when the phase of the feedback clock FBCLK is changed is not directly illustrated in this figure, the update period generally becomes a time corresponding to toggling of an update pulse toggled just after the output signal FINE of the first phase detector 122.
In an example where the phase difference between the source clock REFCLK and the feedback clock FBCLK is greater than the phase difference corresponding to the set delay amount DELAY, the phase of the feedback clock FBCLK is changed by the delay amount corresponding to the two unit delays. In an example where the phase difference between the source clock REFCLK and the feedback clock FBCLK is smaller than the phase difference corresponding to the set delay amount DELAY, the phase of the feedback clock FBCLK is changed by the delay amount smaller than the unit delay. Hence, the size of the set delay amount DELAY is to be set to a size corresponding to the delay amount slightly that is greater than the unit delay. If the size of the set delay amount DELAY is set to an extremely great value, the phase difference between the source clock REFCLK and the feedback clock FBCLK becomes a state that the phase difference between the source clock REFCLK and the feedback clock FBCLK is smaller than that corresponding to the set delay amount DELAY at an extremely fast update timing, and accordingly, an operation is extended in the state that the phase difference between the source clock REFCLK and the feedback clock FBCLK is smaller than the phase difference corresponding to the set delay amount DELAY. Therefore, the size of the set delay amount DELAY is necessarily set to a state having a delay amount slightly greater than the unit delay.
Meanwhile, the time at which the logic level of the phase difference detection signal LOCK_STATE is changed corresponding to the output signals FINE, COARSE1 and COARSE2 of the first to third phase detectors 122, 124 and 126 becomes a time at which an operation pulse PULSE_2 is toggled. More specifically, the time at which the logic level of the phase difference detection signal LOCK_STATE is changed is substantially determined based on the toggling of the operation pulse PULSE_2 after the output signals FINE, COARSE1 and COARSE2 of the first to third phase detectors 122, 124 and 126 are determined. Although not directly illustrated in this figure, the toggling time of the operation pulse PULSE_2 is generally a time later than that of a corresponding update pulse just after the output signal FINE of the first phase detector 122 is generated.
Therefore, the phase of the feedback clock FBCLK is changed in response to the output signal FINE of the first phase detector 122 at the toggling time of the update pulse before the logic level of the phase difference detection signal LOCK_STATE is substantially changed through the output signals FINE, COARSE1 and COARSE2 of the first to third phase detectors 122, 124 and 126 in example (B) where the phase difference between the source clock REFCLK and the feedback clock FBCLK is smaller than the phase difference corresponding to the set delay amount DELAY.
As shown in example (C) where a jitter occurs in example (B) where the phase difference between the source clock REFCLK and the feedback clock FBCLK is smaller than the phase difference corresponding to the set delay amount DELAY, and therefore, the state of example (B) is changed into a state where the phase difference between the source clock REFCLK and the feedback clock FBCLK is greater than the phase difference corresponding to the set delay amount DELAY. In example (C), where a jitter occurs in the source clock REFCLK or the feedback clock FBCLK at the toggling time of the update pulse, the phase of the source clock REFCLK or the feedback clock FBCLK is fluctuated by a delay amount two times greater than the delay amount corresponding to the set delay amount DELAY, and all the output signals FINE, COARSE1 and COARSE2 of the first to third phase detectors 122, 124 and 126 are changed into logic ‘High.’ Therefore, the phase difference detection signal LOCK_STATE is not changed from logic ‘Low’ to logic ‘High’ but continuously maintains the state of logic ‘Low.’
Due to this issue, the phase change interval of the feedback clock FBCLK is continuously maintained as a high state. More specifically, the DLL circuit continuously performs the coarse mode operation. Therefore, the DLL circuit operates only in a manner where the feedback clock FBCLK is continuously delayed. As a result, the delay amount of the variable delay line reaches a limit value, and accordingly, the delay locking operation fails.